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Ordering number : ENA1536
LC87F1JJ2B
Overview
CMOS IC FROM 192K byte, RAM 16384 byte on-chip
8-bit 1-chip Microcontroller with USB-host controller
The LC87F1JJ2B is an 8-bit microcomputer that, centered around a CPU running at a minimum bus cycle time of 83.3ns, integrates on a single chip a number of hardware features such as 192K-byte flash ROM (onboard programmable), 16384-byte RAM, an on-chip debugger, a sophisticated 16-bit timer/counter (may be divided into 8-bit timers), a 16-bit timer (may be divided into 8-bit timers or PWMs), four 8-bit timers with a prescaler, a base timer serving as a realtime clock, 3 channels of synchronous SIO interface with automatic data transfer capabilities, an asynchronous/synchronous SIO interface, a UART interface (full duplex), a full-speed USB interface (host control function), an 8-bit 12-channel AD converter, 2 channels of 12-bit PWM, a system clock frequency divider, an infrared remote control receiver circuit, and a 41-source 10-vector interrupt feature.
Features
Flash ROM * Capable of on-board programming with a wide range of supply voltages: 3.0 to 5.5V * Block-erasable in 128 byte units * Writes data in 2-byte units * 196608 x 8 bits RAM * 16384 x 9 bits Bus Cycle Time * 83.3ns (When CF=12MHz) Note: The bus cycle time here refers to the ROM read speed.
* This product is licensed from Silicon Storage Technology, Inc. (USA), and manufactured and sold by SANYO Semiconductor Co., Ltd.
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment.
Ver.1.02
80509HKIM 20090714-S00004 No.A1536-1/28
LC87F1JJ2B
Minimum Instruction Cycle Time (tCYC) * 250ns (When CF=12MHz) Ports * I/O ports Ports whose I/O direction can be designated in 1-bit units 28 (P10 to P17, P20 to P27, P30 to P34, P70 to P73, PWM0, PWM1, XT2) Ports whose I/O direction can be designated in 4-bit units 8 (P00 to P07) * USB ports 2 (UHD+, UHD-) * Dedicated oscillator ports 2 (CF1, CF2) * Input-only port (also used for oscillation) 1 (XT1) * Reset pin 1 (RES) * Power supply pins 6 (VSS1 to VSS3, VDD1 to VDD3) Timers * Timer 0: 16-bit timer/counter with 2 capture registers. Mode 0: 8-bit timer with an 8-bit programmable prescaler (with two 8-bit capture registers) x 2 channels Mode 1: 8-bit timer with an 8-bit programmable prescaler (with two 8-bit capture registers) + 8-bit counter (with two 8-bit capture registers) Mode 2: 16-bit timer with an 8-bit programmable prescaler (with two 16-bit capture registers) Mode 3: 16-bit counter (with two 16-bit capture registers) * Timer 1: 16-bit timer/counter that supports PWM/toggle outputs Mode 0: 8-bit timer with an 8-bit prescaler (with toggle outputs) + 8-bit timer/ counter with an 8-bit prescaler (with toggle outputs) Mode 1: 8-bit PWM with an 8-bit prescaler x 2 channels Mode 2: 16-bit timer/counter with an 8-bit prescaler (with toggle outputs) (toggle outputs also possible from lower-order 8 bits) Mode 3: 16-bit timer with an 8-bit prescaler (with toggle outputs) (lower-order 8 bits may be used as PWM outputs) * Timer 4: 8-bit timer with a 6-bit prescaler * Timer 5: 8-bit timer with a 6-bit prescaler * Timer 6: 8-bit timer with a 6-bit prescaler (with toggle outputs) * Timer 7: 8-bit timer with a 6-bit prescaler (with toggle outputs) * Base timer 1) The clock is selectable from the subclock (32.768kHz crystal oscillation), system clock, and timer 0 prescaler output. 2) Interrupts programmable in 5 different time schemes SIO * SIO0: Synchronous serial interface 1) LSB first/MSB first mode selectable 2) Transfer clock cycle: 4/3 to 512/3 tCYC 3) Automatic continuous data transmission (1 to 256 bits, specifiable in 1-bit units) (Suspension and resumption of data transmission possible in 1 byte units) * SIO1: 8-bit asynchronous/synchronous serial interface Mode 0: Synchronous 8-bit serial I/O (2- or 3-wire configuration, 2 to 512 tCYC transfer clocks) Mode 1: Asynchronous serial I/O (half-duplex, 8 data bits, 1 stop bit, 8 to 2048 tCYC baudrates) Mode 2: Bus mode 1 (start bit, 8 data bits, 2 to 512 tCYC transfer clocks) Mode 3: Bus mode 2 (start detect, 8 data bits, stop detect) * SIO4: Synchronous serial interface 1) LSB first/MSB first mode selectable 2) Transfer clock cycle: 4/3 to 1020/3 tCYC 3) Automatic continuous data transmission (1 to 8192 bytes, specifiable in 1 byte units) (Suspension and resumption of data transmission possible in 1 byte units or in word units) 4) Auto-start-on-falling-edge function 5) Clock polarity selectable 6) CRC16 calculator circuit built in
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No.A1536-2/28
LC87F1JJ2B
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* SIO9: Synchronous serial interface 1) LSB first/MSB first mode selectable 2) Transfer clock cycle: 4/3 to 1020/3 tCYC 3) Automatic continuous data transmission (1 to 8192 bytes, specifiable in 1 byte units) (Suspension and resumption of data transmission possible in 1 byte units or word units) 4) Auto-start-on-falling-edge function 5) Clock polarity selectable 6) CRC16 calculator circuit built in Full Duplex UART 1) Data length: 7/8/9 bits selectable 2) Stop bits: 1 bit (2 bits in continuous transmission mode) 3) Baud rate: 16/3 to 8192/3 tCYC AD Converter: 8 bits x 12 channels PWM: Multifrequency 12-bit PWM x 2 channels Infrared Remote Control Receiver Circuit 1) Noise rejection function (noise filter time constant: Approx. 120s when the 32.768kHz crystal oscillator is selected as the base clock) 2) Supports data encoding systems such as PPM (Pulse Position Modulation) and Manchester encoding. 3) X'tal HOLD mode release function USB Interface (host control function) 1) Compliant with full-speed (12M bps) specifications 2) Supports 4 transfer types (control transfer, bulk transfer, interrupt transfer, and isochronous transfer). Audio Interface 1) Sampling frequency (fs): 8kHz/11.025kHz/12kHz/16kHz/22.05kHz/24kHz/32kHz/44.1kHz/48kHz 2) Master clock frequency: 256fs/384fs 3) Bit clock selectable: 48fs/64fs 4) Data bit length: 16/18/20/24 bits 5) LSB first/MSB first mode selectable 6) Left-justification/right-justification/I2S format selectable Watchdog Timer * Watchdog timer using external RC circuitry * Interrupt and reset signals selectable Clock Output Function 1) Can output a clock with a clock rate of 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, or 1/64 of the source oscillator clock selected as the system clock. 2) Can output the source oscillation clock for the subclock.
No.A1536-3/28
LC87F1JJ2B
Interrupts * 41 sources, 10 vector addresses 1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests of the level equal to or lower than the current interrupt are not accepted. 2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector address takes precedence.
No. 1 2 3 4 5 6 7 8 9 10 Vector Address 00003H 0000BH 00013H 0001BH 00023H 0002BH 00033H 0003BH 00043H 0004BH Level X or L X or L H or L H or L H or L H or L H or L H or L H or L H or L INT0 INT1 INT2/T0L/INT4/UHC bus active/remote control signal receive INT3/INT5/base timer T0H/INT6/UHC device attach/UHC device detach/UHC resume T1L/T1H/INT7/SIO9/AIF start SIO0/UART1 receive SIO1/SIO4/UART1 transmit/AIF end ADC/T6/T7/UHC-ACK/UHC-NAK/UHC error/UHC-STALL Port 0/PWM0/PWM1/T4/T5/UHC-SOF/DMCOPY/AIF error Interrupt Source
* Priority levels X > H > L * Of interrupts of the same level, the one with the smallest vector address takes precedence. Subroutine Stack Levels: 8192 levels maximum (The stack is allocated in RAM.) High-speed Multiplication/Division Instructions * 16 bits x 8 bits (5 tCYC execution time) * 24 bits x 16 bits (12 tCYC execution time) * 16 bits / 8 bits (8 tCYC execution time) * 24 bits / 16 bits (12 tCYC execution time) Oscillation and PLL Circuits * RC oscillation circuit (internal): * CF oscillation circuit: * Crystal oscillation circuit: * PLL circuit (internal):
For system clock For system clock For system clock, and realtime clock For USB interface (see Fig.5) and audio interface (see Fig. 6)
No.A1536-4/28
LC87F1JJ2B
Standby Function * HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation. 1) Oscillation is not halted automatically. 2) There are three ways of releasing the HALT mode. (1) Setting the reset pin to the lower level. (2) System resetting by watchdog timer (3) Generating an interrupt * HOLD mode: Suspends instruction execution and the operation of the peripheral circuits. 1) The PLL base clock generator, CF, RC and crystal oscillators automatically stop operation. 2) There are five ways of releasing the HOLD mode. (1) Setting the reset pin to the lower level (2) System resetting by watchdog timer (3) Having an interrupt source established at one of the INT0, INT1, INT2, INT4, and INT5 pins * The INT0 and INT1 pins must be configured only for level detection. (4) Having an interrupt source established at port 0 (5) Having an bus active interrupt source established in the USB host control circuit * X'tal HOLD mode: Suspends instruction execution and the operation of the peripheral circuits except the base timer. 1) The PLL base clock generator, CF and RC oscillator automatically stop operation. 2) The state of crystal oscillation established when the X'tal HOLD mode is entered is retained. 3) There are seven ways of releasing the X'tal HOLD mode. (1) Setting the reset pin to the low level (2) System resetting by watchdog timer (3) Having an interrupt source established at one of the INT0, INT1, INT2, INT4, and INT5 pins * The INT0 and INT1 pins must be configured only for level detection. (4) Having an interrupt source established at port 0 (5) Having an interrupt source established in the base timer circuit (6) Having an bus active interrupt source established in the USB host control circuit (7) Having an interrupt source established in the infrared remote controller receiver circuit Package Form * SQFP48(7x7): Lead-free type Development Tools * On-chip debugger: TCB87- type B + LC87F1JJ2B Flash ROM Programming Boards
Package SQFP48(7x7) Programming board W87F55256SQ
Flash ROM Programmer
Maker Flash Support Group, Inc. (FSG) Flash Support Group, Inc. (FSG) + SANYO(Note 1) Single/ganged SANYO Onboard single/ganged Onboard single/ganged Single Model AF9708/ AF9709/AF9709B/AF9709C (including Ando Electric Co., Ltd. models) AF9101/AF9103(main unit) (FSG) SIB87(interface driver) (SANYO) SKK/SKK Type B (SANYO FWS) SKK-DBG Type B (SANYO FWS) Application version: 1.04 or later Chip data version: 2.17 or later LC87F1JJ2 (Note 2) LC87F1JJ2A Rev. 03.12 or later LC87F1JJ2A Supported Version Device
Note 1: PC-less standalone onboard programming is possible using the FSG onboard programmer (AF9101/AF9103) and the serial interface driver (SIB87) provided by SANYO in pair. Note 2: Dedicated programming device and program are required depending on the programming conditions. Contact SANYO or FSG if you have any questions or difficulties regarding this matter.
No.A1536-5/28
LC87F1JJ2B
Package Dimensions
unit : mm (typ) 3163B
9.0 7.0 36 37 25 24
48 1 0.5 (0.75) 12 0.18
13
7.0 9.0
0.15
1.7max
0.1
(1.5)
SANYO : SQFP48(7X7)
Pin Assignment
P27/INT5/SCK9 P26/INT5/SI9/WR9 P25/INT5/SO9/RD9 P24/INT5/INT7/SCK4 P23/INT4/SI4/WR P22/INT4/SO4/RD P21/INT4 P20/INT4/INT6 P07/AN7/T7O/LRCK P06/AN6/T6O/BCLK P05/AN5/CKO/SDAT P04/AN4/DBGP2 UHDUHD+ VDD3 VSS3 P34/UFILT P33/AFILT P32 P31/URX1 P30/UTX1 P70/INT0/T0LCP/AN8 P71/INT1/T0HCP/AN9 P72/INT2/T0IN 37 38 39 40 41 42 43 44 45 46 47 48 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13
0.5
LC87F1JJ2B
P03/AN3/DBGP1 P02/AN2/DBGP0 P01/AN1 P00/AN0 VSS2 VDD2 PWM0/MCLKO PWM1/MCLKI P17/T1PWMH/BUZ P16/T1PWML P15/SCK1 P14/SI1/SB1
P73/INT3/T0IN/RMIN RES XT1/AN10 XT2/AN11 VSS1 CF1 CF2 VDD1 P10/SO0 P11/SI0/SB0 P12/SCK0 P13/SO1
1 2 3 4 5 6 7 8 9 10 11 12
Top view
SANYO: SQFP48(7x7) "Lead-free type"
No.A1536-6/28
LC87F1JJ2B
SQFP48 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 NAME P73/INT3/T0IN/RMIN RES XT1/AN10 XT2/AN11 VSS1 CF1 CF2 VDD1 P10/SO0 P11/SI0/SB0 P12/SCK0 P13/SO1 P14/SI1/SB1 P15/SCK1 P16/T1PWML P17/T1PWMH/BUZ PWM1/MCLKI PWM0/MCLKO VDD2 VSS2 P00/AN0 P01/AN1 P02/AN2/DBGP0 P03/AN3/DBGP1 SQFP48 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 NAME P04/AN4/DBGP2 P05/AN5/CKO/SDAT P06/AN6/T6O/BCLK P07/AN7/T7O/LRCK P20/INT4/INT6 P21/INT4 P22/INT4/SO4/RD P23/INT4/SI4/WR P24/INT5/INT7/SCK4 P25/INT5/SO9/RD9 P26/INT5/SI9/WR9 P27/INT5/SCK9 UHDUHD+ VDD3 VSS3 P34/UFILT P33/AFILT P32 P31/URX1 P30/UTX1 P70/INT0/T0LCP/AN8 P71/INT1/T0HCP/AN9 P72/INT2/T0IN
No.A1536-7/28
LC87F1JJ2B
System Block Diagram
Interrupt control
IR
PLA
Standby control
FROM
CF RC X'tal
USB PLL Clock generator PC
SIO0
Bus interface
ACC
SIO1
Port 0
B register
SIO4
Port 1
C register
SIO9
Port 2 ALU
Timer 0
Port 3
Timer 1
Port 7 INT0 to INT7 noise filter UART1
PSW
Timer 4
RAR
Timer 5
RAM
Timer 6
Audio interface
Stack pointer
Timer 7
ADC
Infrared remote control receiver circuit
Watchdog timer
Base timer
On-chip debugger
PWM0
PWM1
USB host
No.A1536-8/28
LC87F1JJ2B
Pin Description
Pin Name VSS1,VSS2, VSS3 VDD1, VDD2 VDD3 Port 0 P00 to P07 I/O I/O - power supply + power supply USB reference voltage * 8-bit I/O ports * I/O specifiable in 4-bit units * Pull-up resistors can be turned on and off in 4-bit units. * HOLD release input * Port 0 interrupt input * Pin functions AD converter input ports: AN0 to AN7(P00 to P07) On-chip debugger pins: DBGP0 to DBGP2(P02 to P04) P05: System clock output/audio interface SDAT input/output P06: Timer 6 toggle output/audio interface BCLK input/output P07: Timer 7 toggle output/audio interface LRCK input/output Port 1 P10 to P17 I/O * 8-bit I/O ports * I/O specifiable in 1-bit units * Pull-up resistors can be turned on and off in 1-bit units. * Pin functions P10: SIO0 data output P11: SIO0 data input/bus input/output P12: SIO0 clock input/output P13: SIO1 data output Port 2 P20 to P27 I/O * 8-bit I/O ports * I/O specifiable in 1-bit units * Pull-up resistors can be turned on and off in 1-bit units. * Pin functions P20 to P23: INT4 input/HOLD release input/timer 1 event input/timer 0L capture input/ timer 0H capture input P24 to P27: INT5 input/HOLD release input/timer 1 event input/timer 0L capture input/ timer 0H capture input P20: INT6 input/timer 0L capture 1 input P22: SIO4 data input/output/parallel interface RD output P23: SIO4 data input/output/parallel interface WR output P24: SIO4 clock input/output/INT7 input/timer 0H capture 1 input P25: SIO9 data input/output/parallel interface RD9 output P26: SIO9 data input/output/parallel interface WR9 output P27: SIO9 clock input/output Interrupt acknowledge types Rising INT4 INT5 INT6 INT7 * 5-bit I/O ports * I/O specifiable in 1-bit units * Pull-up resistors can be turned on and off in 1-bit units. * Pin functions P30: UART1 transmit P31: UART1 receive P33: Audio interface PLL filter circuit connection pin (See Fig. 6.) P34: USB interface PLL filter circuit connection pin (See Fig. 5.) enable enable enable enable Falling enable enable enable enable Rising & Falling enable enable enable enable H level disable disable disable disable L level disable disable disable disable P14: SIO1 data input/bus input/output P15: SIO1 clock input/output P16: Timer 1 PWML output P17: Timer 1 PWMH output/beeper output Yes Yes Description Option No No Yes Yes
Port 3 P30 to P34
I/O
Yes
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No.A1536-9/28
LC87F1JJ2B
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Pin Name Port 7 P70 to P73 I/O I/O * 4-bit I/O ports * I/O specifiable in 1-bit units * Pull-up resistors can be turned on and off in 1-bit units. * Pin functions P70: INT0 input/HOLD release input/timer 0L capture input/watchdog timer output P71: INT1 input/HOLD release input/timer 0H capture input P72: INT2 input/HOLD release input/timer 0 event input/timer 0L capture input/ high speed clock counter input P73: INT3 input (input with noise filter)/timer 0 event input/timer 0H capture input/ infrared remote control receiver input AD converter input ports: AN8(P70), AN9(P71) Interrupt acknowledge types Rising INT0 INT1 INT2 INT3 enable enable enable enable Falling enable enable enable enable Rising & Falling disable disable enable enable H level enable enable disable disable L level enable enable disable disable Description Option No
PWM0 PWM1
I/O
PWM0, PWM1 output ports General-purpose input port * Pin functions PWM0: Audio interface master clock output PWM1: Audio interface master clock input
No
UHDUHD+ RES XT1
I/O I/O I I
USB data I/O pin UHD-/general-purpose I/O port USB data I/O pin UHD+/general-purpose I/O port Reset pin * 32.768kHz crystal oscillator input * Pin functions General-purpose input port AD converter input port: AN10 Must be connected to VDD1 when not to be used. * 32.768kHz crystal oscillator output * Pin functions General-purpose input port AD converter input port: AN11 Must be configured for oscillation and kept open if not to be used.
No No No No
XT2
I/O
No
CF1 CF2
I O
Ceramic/crystal resonator input Ceramic/crystal resonator output
No No
Port Output Types
The table below lists the types of port outputs and the presence/absence of a pull-up resistor. Data can be read into any input port even if it is in the output mode.
Port Name P00 to P07 Option Selected in Units of 1 bit Option Type 1 2 P10 to P17 P20 to P27 P30 to P34 P70 P71 to P73 PWM0, PWM1 UHD+, UHDXT1 XT2 No No No No No No Nch-open drain CMOS CMOS CMOS Input only 32.768kHz crystal resonator output (Nch-open drain when in general-purpose output mode) Programmable Programmable No No No No 1 bit 1 2 CMOS Nch-open drain CMOS Nch-open drain Output Type Pull-up Resistor Programmable (Note 1) No Programmable Programmable
Note 1: Programmable pull-up resistors for port 0 are controlled in 4 bit units (P00 to 03, P04 to 07).
No.A1536-10/28
LC87F1JJ2B
User Options
Option Name Port output type P00 to P07 1 bit Type Flash ROM Version Option Selected in Units of CMOS Nch-open drain CMOS P10 to P17 1 bit Nch-open drain CMOS P20 to P27 1 bit Nch-open drain CMOS P30 to P34 Program start address USB Regulator USB Regulator USB Regulator (at HOLD mode) USB Regulator (at HALT mode) 1 bit Nch-open drain 00000h 1FE00h Use Nonuse Use Nonuse Use Nonuse Setting
Power Pin Treatment
Connect the IC as shown below to minimize the noise input to the VDD1 pin and extend the backup period. Be sure to electrically short the VSS1, VSS2, and VSS3 pins. Example 1: When the microcontroller is in the backup state in the HOLD mode, the power to sustain the high level of output ports is supplied by their backup capacitors.
LSI For backup Power supply VDD1
VDD2 VDD3
VSS1 VSS2 VSS3
Example 2: The high level output at ports is not sustained and unstable in the HOLD backup mode.
LSI For backup Power supply VDD1
VDD2 VDD3
VSS1 VSS2 VSS3
No.A1536-11/28
LC87F1JJ2B
USB Reference Power Option
When a voltage 4.5 to 5.5V is supplied to VDD1 and the internal USB reference voltage circuit is activated, the reference voltage for USB port output is generated. The active/inactive state of the reference voltage circuit can be switched by optional settings. The procedure for marking the optional settings is described below.
(1) Option settings USB regulator USB regulator in HOLD mode USB regulator in HALT mode Reference voltage circuit state Normal mode HOLD mode HALT mode Use Use Use Active Active Active (2) Use Nonuse Nonuse Active Inactive Inactive (3) Use Nonuse Use Active Inactive Active (4) Nonuse Nonuse Nonuse Inactive Inactive Inactive
* When the USB reference voltage circuit is made inactive, the level of the reference voltage for USB port output is equal to VDD1. * Selection (2) or (3) can be used to set the reference voltage circuit inactive in HOLD or HALT mode. * When the reference voltage circuit is activated, the current drain increases by approximately 100A compared with when the reference voltage circuit is inactive. Circuit example 1: When VDD1=VDD2=3.3V * Inactivating the reference voltage circuit (selection (4)). * Connecting VDD3 to VDD1 and VDD2.
LSI Power supply 3.3V VDD1 UHD+ 33 UHDVDD2 5pF 2.2F
*1
To USB connector
15k
VDD3
UFILT 0
VSS1 VSS2 VSS3 2.2F
*1: Needs adjustment on target board. Circuit example 2: When VDD1=VDD2=5.0V * Activating the reference voltage circuit (selection (1)). * Isolating VDD3 from VDD1 and VDD2, and connecting capacitor between VDD3 and VSS.
LSI Power supply 5V VDD1 UHD+ 33 UHDVDD2 5pF VDD3 2.2F 0.1F VSS1 VSS2 VSS3 2.2F UFILT 0 15k To USB connector
No.A1536-12/28
LC87F1JJ2B
Absolute Maximum Ratings at Ta = 25C, VSS1 = VSS2 = VSS3 = 0V
Parameter Maximum supply voltage Input voltage Input/output voltage Peak output current IOPH(2) IOPH(3) PWM0, PWM1 Port 3 P71 to P73 Average High level output current output current (Note 1-1) IOMH(2) IOMH(3) PWM0, PWM1 Port 3 P71 to P73 Total output current IOAH(2) IOAH(3) IOAH(4) IOAH(5) Peak output current IOPL(2) IOPL(3) Average Low level output current output current (Note 1-1) IOML(2) IOML(3) Total output current IOAL(2) IOAL(3) IOAL(4) IOAL(5) Allowable power dissipation Operating ambient temperature Storage ambient temperature Tstg Topr -40 -55 Pd max Port 1 PWM0, PWM1 Ports 0, 1, 2 PWM0, PWM1 Ports 3, 7 XT2 UHD+, UHDSQFP48(7x7) IOAL(1) IOML(1) IOPL(1) Port 1 PWM0, PWM1 Ports 0, 1, 2 PWM0, PWM1 Port 3 P71 to P73 UHD+, UHDP02 to P07 Ports 1, 2 PWM0, PWM1 P00, P01 Ports 3, 7 XT2 P02 to P07 Ports 1, 2 PWM0, PWM1 P00, P01 Ports 3, 7 XT2 Ports 0, 2 Total current of all applicable pins Total current of all applicable pins Total current of all applicable pins Total current of all applicable pins Total current of all applicable pins Ta=-40 to +85C Per 1 applicable pin Per 1 applicable pin 20 7.5 45 45 80 15 25 140 +85 C +125 mW Per 1 applicable pin 15 Per 1 applicable pin Per 1 applicable pin 30 10 IOAH(1) Ports 0, 2 IOMH(1) Ports 0, 1, 2 IOPH(1) VI(1) VIO(1) XT1, CF1 Ports 0, 1, 2, 3, 7 PWM0, PWM1 XT2 Ports 0, 1, 2 * When CMOS output type is selected * Per 1 applicable pin Per 1 applicable pin * When CMOS output type is selected * Per 1 applicable pin * When CMOS output type is selected * Per 1 applicable pin Per 1 applicable pin * When CMOS output type is selected * Per 1 applicable pin Total current of all applicable pins Total current of all applicable pins Total current of all applicable pins Total current of all applicable pins Total current of all applicable pins Per 1 applicable pin 20 -25 -25 -45 -10 -25 mA -3 -15 -7.5 -5 -20 -10 -0.3 VDD+0.3 Symbol VDD max Pin/Remarks VDD1, VDD2, VDD3 Conditions VDD[V] VDD1= VDD2= VDD3 min -0.3 -0.3 Specification typ max +6.5 VDD+0.3 V unit
Note 1-1: The average output current is an average of current values measured over 100ms intervals.
No.A1536-13/28
LC87F1JJ2B
Allowable Operating Conditions at Ta = -40C to +85C, VSS1 = VSS2 = VSS3 = 0V
Parameter Operating supply voltage (Note 2-1) Memory sustaining supply voltage High level input voltage VIH(1) Ports 0, 1, 2, 3 P71 to P73 P70 port input/ interrupt side PWM0, PWM1 VIH(2) VIH(3) Low level input voltage VIL(2) VIL(3) VIL(4) VIL(5) VIL(6) Instruction cycle time (Note 2-2) External system clock frequency FEXCF(1) CF1 tCYC Except in onboard programming mode * CF2 pin open * System clock frequency division ratio=1/1 * External system clock duty =505% * CF2 pin open * System clock frequency division ratio=1/1 * External system clock duty =505% Oscillation frequency range (Note 2-3) FmRC FsX'tal XT1, XT2 FmCF(2) CF1, CF2 FmCF(1) CF1, CF2 When 12MHz ceramic oscillation See Fig. 1. When 6MHz ceramic oscillation See Fig. 1. Internal RC oscillation 32.768kHz crystal oscillation See Fig. 2. 3.0 to 5.5 2.7 to 5.5 2.7 to 5.5 2.7 to 5.5 0.3 12 6 1.0 32.768 2.0 kHz MHz 2.7 to 5.5 0.1 6 MHz 3.0 to 5.5 0.1 12 Port 70 watchdog timer side XT1, XT2, CF1, RES VIL(1) Port 70 watchdog timer side XT1, XT2, CF1, RES Ports 1, 2, 3 P71 to P73 P70 port input/ interrupt side Port 0 PWM0, PWM1 2.7 to 5.5 2.7 to 5.5 4.0 to 5.5 2.7 to 4.0 4.0 to 5.5 2.7 to 4.0 2.7 to 5.5 2.7 to 5.5 3.0 to 5.5 2.7 to 5.5 0.9VDD 0.75VDD VSS VSS VSS VSS VSS VSS 0.245 0.490 VDD V VDD 0.1VDD +0.4 0.2VDD 0.15VDD +0.4 0.2VDD 0.8VDD -1.0 0.25VDD 200 200 s 2.7 to 5.5 0.3VDD +0.7 VDD VHD VDD1=VDD2=VDD3 Symbol VDD(1) Pin/Remarks VDD1=VDD2=VDD3 Conditions 0.245s tCYC 200s 0.490s tCYC 200s Except in onboard programming mode RAM and register contents sustained in HOLD mode. 2.0 5.5 Specification VDD[V] min 3.0 2.7 typ max 5.5 5.5 unit
Note 2-1: VDD must be held greater than or equal to 3.0V in the flash ROM onboard programming mode. Note 2-2: Relationship between tCYC and oscillation frequency is 3/FmCF at a division ratio of 1/1 and 6/FmCF at a division ratio of 1/2. Note 2-3: See oscillation characteristics examples.
No.A1536-14/28
LC87F1JJ2B
Electrical Characteristics at Ta = -40C to +85C, VSS1 = VSS2 = VSS3 = 0V
Parameter High level input current Symbol IIH(1) Pin/Remarks Ports 0, 1, 2, 3 Port 7 RES PWM0, PWM1 UHD+, UHDIIH(2) IIH(3) Low level input current IIL(1) XT1, XT2 CF1 Ports 0, 1, 2, 3 Port 7 RES PWM0, PWM1 UHD+, UHDIIL(2) IIL(3) High level output voltage VOH(1) VOH(2) VOH(3) VOH(4) VOH(5) VOH(6) Low level output voltage VOL(1) VOL(2) VOL(3) VOL(4) VOL(5) VOL(6) VOL(7) VOL(8) Pull-up resistance Rpu(1) Rpu(2) Hysteresis voltage Pin capacitance VHYS CP Ports 0, 1, 2, 3 Port 7 RES Port 1, 2, 3, 7 All pins For pins other than that under test: VIN=VSS f=1MHz Ta=25C 2.7 to 5.5 10 pF Ports 0, 1, 2 PWM0, PWM1 XT2 Ports 3, 7 PWM0, PWM1 P05 to P07 (Note 3-1) P00, P01 XT1, XT2 CF1 Ports 0, 1, 2, 3 P71 to P73 Conditions VDD[V] Output disabled Pull-up resistor off VIN=VDD (Including output Tr's off leakage current) Input port configuration VIN=VDD VIN=VDD Output disabled Pull-up resistor off VIN=VSS (Including output Tr's off leakage current) Input port configuration VIN=VSS VIN=VSS IOH=-1mA IOH=-0.4mA IOH=-0.2mA IOH=-10mA IOH=-1.6mA IOH=-1mA IOL=30mA IOL=5mA IOL=2.5mA IOL=10mA IOL=1.6mA IOL=1mA IOL=1.6mA IOL=1mA VOH=0.9VDD 2.7 to 5.5 2.7 to 5.5 4.5 to 5.5 3.0 to 5.5 2.7 to 5.5 4.5 to 5.5 3.0 to 5.5 2.7 to 5.5 4.5 to 5.5 3.0 to 5.5 2.7 to 5.5 4.5 to 5.5 3.0 to 5.5 2.7 to 5.5 3.0 to 5.5 2.7 to 5.5 4.5 to 5.5 2.7 to 4.5 2.7 to 5.5 15 18 35 50 0.1VDD -1 -15 VDD-1 VDD-0.4 VDD-0.4 VDD-1.5 VDD-0.4 VDD-0.4 1.5 0.4 0.4 1.5 0.4 0.4 0.4 0.4 80 150 V k V 2.7 to 5.5 -1 2.7 to 5.5 2.7 to 5.5 1 15 A 2.7 to 5.5 1 min Specification typ max unit
Note 3-1: When the CKO system clock output function (P05) or audio interface output function (P05 to P07) is used.
No.A1536-15/28
LC87F1JJ2B
Serial I/O Characteristics at Ta = -40C to +85C, VSS1 = VSS2 = VSS3 = 0V
1. SIO0 Serial I/O Characteristics (Note 4-1-1)
Parameter Frequency Low level pulse width High level pulse width tSCKHA(1a) * Continuous data transfer mode * USB, AIF, SIO4, SIO9, and DMCOPY not used at the same time. Input clock * See Fig. 9. * (Note 4-1-2) tSCKHA(1b) * Continuous data transfer mode * USB used at the same time. * AIF, SIO4, SIO9, and DMCOPY not used at the same time. * See Fig. 9. * (Note 4-1-2) tSCKHA(1c) * Continuous data transfer mode * USB, AIF, SIO4, SIO9, and DMCOPY used at the same time. * See Fig. 9. Serial clock * (Note 4-1-2) Frequency Low level pulse width High level pulse width tSCKHA(2a) * Continuous data transfer mode * USB, AIF, SIO4, SIO9, and DMCOPY not used at the same time. * When CMOS output type is Output clock selected * See Fig. 9. tSCKHA(2b) * Continuous data transfer mode * USB used at the same time. * AIF, SIO4, SIO9, and DMCOPY not used at the same time. * When CMOS output type is selected. * See Fig.9. tSCKHA(2c) * Continuous data transfer mode * USB, AIF, SIO4, SIO9, and DMCOPY used at the same time * When CMOS output type is selected * See Fig.9. tSCKH(2) +2tCYC tSCKH(2) + (25/3)tCYC tSCKH(2) +2tCYC tSCKH(2) + (19/3)tCYC tCYC 2.7 to 5.5 tSCKH(2) +2tCYC tSCKH(2) + (10/3)tCYC tSCKH(2) tSCK(2) tSCKL(2) SCK0(P12) * When CMOS output type is selected * See Fig. 9. 4/3 1/2 tSCK 1/2 9 7 2.7 to 5.5 tCYC 4 tSCKH(1) Symbol tSCK(1) tSCKL(1) Pin/ Remarks SCK0(P12) See Fig. 9. Conditions VDD[V] min 2 1 1 Specification typ max unit
Note 4-1-1: These specifications are theoretical values. Margins must be allowed according to the actual operating conditions. Note 4-1-2: In an application where the serial clock input is to be used in the continuous data transfer mode, the time from SI0RUN being set when serial clock is high to the falling edge of the first serial clock must be longer than tSCKHA.
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No.A1536-16/28
LC87F1JJ2B
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Parameter Data setup time Serial input Symbol tsDI(1) Pin/ Remarks SB0(P11), SI0(P11) Data hold time thDI(1) Conditions VDD[V] * Must be specified with respect to rising edge of SIOCLK. * See Fig. 9. 2.7 to 5.5 0.03 Output delay Input clock time tdDO(2) tdDO(1) SO0(P10), SB0(P11) * Continuous data transfer mode * (Note 4-1-3) * Synchronous 8-bit mode * (Note 4-1-3) 2.7 to 5.5 tdDO(3) Output clock (Note 4-1-3) (1/3)tCY C +0.05 (1/3)tCY C +0.05 1tCYC +0.05 s 0.03 min Specification typ max unit
Note 4-1-3: Must be specified with respect to falling edge of SIOCLK. Must be specified as the time to the beginning of output state change in open drain output mode. See Fig. 9. 2. SIO1 Serial I/O Characteristics (Note 4-2-1)
Parameter Frequency Input clock Low level pulse width High level pulse width Frequency Output clock Low level pulse width High level pulse width Data setup time Serial input tsDI(2) SB1(P14), SI1(P14) Data hold time thDI(2) * Must be specified with respect to rising edge of SIOCLK. * See Fig. 9. 2.7 to 5.5 0.03 Output delay time Serial output tdDO(4) SO1(P13), SB1(P14) * Must be specified with respect to falling edge of SIOCLK. * Must be specified as the time to the beginning of output state change in open drain output mode. * See Fig. 9. 2.7 to 5.5 (1/3)tCYC +0.05 s 0.03 tSCKH(4) tSCK(4) tSCKL(4) SCK1(P15) * When CMOS output type is selected * See Fig. 9. 2.7 to 5.5 tSCKH(3) Symbol tSCK(3) tSCKL(3) Pin/ Remarks SCK1(P15) See Fig. 9. Conditions VDD[V] min 2 2.7 to 5.5 1 tCYC 1 2 1/2 tSCK 1/2 Specification typ max unit
Note 4-2-1: These specifications are theoretical values. Margins must be allowed according to the actual operating conditions.
Serial clock
Serial output
No.A1536-17/28
LC87F1JJ2B
3. SIO4 Serial I/O Characteristics (Note 4-3-1)
Parameter Frequency Low level pulse width High level pulse width tSCKHA(5a) * USB, SIO0 continuous transfer mode, AIF, SIO9, and DMCOPY not used at the same time. Input clock * See Fig. 9. * (Note 4-3-2) tSCKHA(5b) * USB used at the same time * SIO0 continuous transfer mode, AIF, SIO9, and DMCOPY not used at the same time. * See Fig. 9. * (Note 4-3-2) tSCKHA(5c) * USB, SIO0 continuous transfer mode, SIO9, and DMCOPY used at the same time. * AIF not used at the same time. * See Fig. 9. Serial clock * (Note 4-3-2) Frequency Low level pulse width High level pulse width (Note 4-3-3) tSCKHA(6a) * USB, SIO0 continuous transfer mode, AIF, SIO9, and DMCOPY not used at the same time. * When CMOS output type is selected. Output clock * See Fig. 9. tSCKHA(6b) * USB used at the same time. * SIO0 continuous transfer mode, AIF, SIO9, and DMCOPY not used at the same time. * When CMOS output type is selected. * See Fig. 9. tSCKHA(6c) * USB, SIO0 continuous transfer mode, SIO9, and DMCOPY used at the same time. * AIF not used at the same time. * When CMOS output type is selected. * See Fig. 9. tSCKH(6) + (5/3)tCYC tSCKH(6) + (34/3)tCYC 2.7 to 5.5 tSCKH(6) + (5/3)tCYC tSCKH(6) + (19/3)tCYC tCYC tSCKH(6) + (5/3)tCYC tSCKH(6) + (10/3)tCYC tSCKH(6) tSCK(6) tSCKL(6) SCK4(P24) * When CMOS output type is selected. * See Fig. 9. 4/3 1/2 tSCK 1/2 12 7 2.7 to 5.5 tCYC 4 tSCKH(5) Symbol tSCK(5) tSCKL(5) Pin/ Remarks SCK4(P24) See Fig. 9. Conditions VDD[V] min 2 1 1 Specification typ max unit
Note 4-3-1: These specifications are theoretical values. Margins must be allowed according to the actual operating conditions. Note 4-3-2: In an application where the serial clock input is to be used in the continuous data transfer mode, the period from the time SI4RUN is set with the serial clock set high to the falling edge of the first serial clock must be longer than tSCKHA. Note 4-3-3: When using the serial clock output, make sure that the load at the SCK4 (P24) pin meets the following conditions: Clock rise time tSCKR < 0.037s (see Figure 12.) at Ta=+25C, VDD=3.3V
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No.A1536-18/28
LC87F1JJ2B
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Parameter Data setup time Serial input Symbol tsDI(3) Pin/ Remarks SO4(P22), SI4(P23) Data hold time thDI(3) Conditions VDD[V] * Must be specified with respect to rising edge of SIOCLK. * See Fig. 9 2.7 to 5.5 0.03 Output delay time Serial output tdDO(5) SO4(P22), SI4(P23) * Must be specified with respect to falling edge of SIOCLK. * Must be specified as the time to the beginning of output state change in open drain output mode. * See Fig. 9. 2.7 to 5.5 (1/3)tCYC +0.05 s 0.03 min Specification typ max unit
4. SIO9 Serial I/O Characteristics (Note 4-4-1)
Parameter Frequency Low level pulse width High level pulse width tSCKHA(7a) * USB, SIO0 continuous transfer mode, AIF, SIO4, and DMCOPY not used at the same time. Serial clock Input clock * See Fig. 9. * (Note 4-4-2) tSCKHA(7b) * USB used at the same time. * SIO0 continuous transfer mode, AIF, SIO4, and DMCOPY not used at the same time. * See Fig. 9. * (Note 4-4-2) tSCKHA(7c) * USB, SIO0 continuous transfer mode, SIO4, and DMCOPY used at the same time. * AIF not used at the same time. * See Fig. 9. * (Note 4-4-2) 15 7 2.7 to 5.5 tCYC 4 tSCKH(7) Symbol tSCK(7) tSCKL(7) Pin/ Remarks SCK9(P27) See Fig. 9. Conditions VDD[V] min 2 1 1 Specification typ max unit
Note 4-4-1: These specifications are theoretical values. Margins must be allowed according to the actual operating conditions. Note 4-4-2: In an application where the serial clock input is to be used in the continuous data transfer mode, the period from the time SI9RUN is set with the serial clock set high to the falling edge of the first serial clock must be longer than tSCKHA.
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No.A1536-19/28
LC87F1JJ2B
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Parameter Frequency Low level pulse width High level pulse width (Note 4-4-3) tSCKHA(8a) * USB, SIO0 continuous transfer mode, AIF, SIO4, and DMCOPY not used at the same time. * When CMOS output type is selected. Output clock Serial clock * See Fig. 9. tSCKHA(8b) * USB used at the same time. * SIO0 continuous transfer mode, AIF, SIO4, and DMCOPY not used at the same time. * When CMOS output type is selected * See Fig. 9. tSCKHA(8c) * USB, SIO0 continuous transfer mode , SIO4, and DMCOPY used at the same time. * AIF not used at the same time. * When CMOS output type is selected. * See Fig. 9. Data setup time Serial input tsDI(4) SO9(P25), SI9(P26) * Must be specified with respect to rising edge of SIOCLK. * See Fig. 9. Data hold time thDI(4) 0.03 * Must be specified with respect to falling edge of SIOCLK. * Must be specified as the time to the beginning of output state change in open drain output mode * See Fig. 9. 2.7 to 5.5 (1/3)tCYC +0.05 s 2.7 to 5.5 0.03 tSCKH(8) + (5/3)tCYC tSCKH(8) + (43/3)tCYC 2.7 to 5.5 tSCKH(8) + (5/3)tCYC tSCKH(8) + (19/3)tCYC tCYC tSCKH(8) + (5/3)tCYC tSCKH(8) + (10/3)tCYC tSCKH(8) Symbol tSCK(8) tSCKL(8) Pin/ Remarks SCK9(P27) Conditions VDD[V] * When CMOS output type is selected. * See Fig. 9. min 4/3 1/2 tSCK 1/2 Specification typ max unit tCYC
Output delay time Serial output
tdDO(6)
SO9(P25), SI9(P26)
Note 4-4-3: When using the serial clock output, make sure that the load at the SCK9 (P27) pin meets the following conditions: Clock rise time tSCKR < 0.037s (see Figure 12.) at Ta=+25C, VDD=3.3V
No.A1536-20/28
LC87F1JJ2B
Pulse Input Conditions at Ta = -40C to +85C, VSS1 = VSS2 = VSS3 = 0V
Parameter High/low level pulse width Symbol tPIH(1) tPIL(1) Pin/Remarks INT0(P70), INT1(P71), INT2(P72), INT4(P20 to P23), INT5(P24 to P27), INT6(P20), INT7(P24) tPIH(2) tPIL(2) tPIH(3) tPIL(3) tPIH(4) tPIL(4) tPIL(5) tPIL(6) INT3(P73) when noise filter time constant is 1/1 INT3(P73) when noise filter time constant is 1/32 INT3(P73) when noise filter time constant is 1/128 RMIN(P73) RES * Interrupt source flag can be set. * Event inputs for timer 0 are enabled. * Interrupt source flag can be set. * Event inputs for timer 0 are enabled. * Interrupt source flag can be set. * Event inputs for timer 0 are enabled. Recognized by the infrared remote control receiver circuit as a signal Resetting is enabled. 2.7 to 5.5 2.7 to 5.5 4 200 RMCK (Note 5-1) s 2.7 to 5.5 256 2.7 to 5.5 64 2.7 to 5.5 2 tCYC Conditions VDD[V] * Interrupt source flag can be set. * Event inputs for timer 0 or 1 are enabled. 2.7 to 5.5 1 min Specification typ max unit
Note 5-1: Represents the period of the reference clock (1 tCYC to 128 tCYC or the source frequency of the subclock) for the infrared remote control receiver circuit.
AD Converter Characteristics at Ta = -40C to +85C, VSS1 = VSS2 = VSS3 = 0V
Parameter Resolution Absolute accuracy Conversion time TCAD Symbol N ET Pin/Remarks AN0(P00) to AN7(P07), AN8(P70), AN9(P71), AN10(XT1), AN11(XT2) AD conversion time=32xtCYC (when ADCR2=0) (Note 6-2) 4.5 to 5.5 (Note 6-1) Conditions VDD[V] 3.0 to 5.5 3.0 to 5.5 15.68 (tCYC= 0.490s) 23.52 3.0 to 5.5 AD conversion time=64xtCYC (when ADCR2=1) (Note 6-2) 4.5 to 5.5 (tCYC= 0.735s) 18.82 (tCYC= 0.294s) 47.04 3.0 to 5.5 Analog input voltage range Analog port input current IAINH IAINL VAIN=VDD VAIN=VSS VAIN (tCYC= 0.735s) 3.0 to 5.5 3.0 to 5.5 3.0 to 5.5 -1 VSS min Specification typ 8 max unit bit
1.5
97.92 (tCYC= 3.06s) 97.92 (tCYC= 3.06s) 97.92 (tCYC= 1.53s) 97.92 (tCYC= 1.53s) VDD 1
LSB
s
V A
Note 6-1: The quantization error (1/2LSB) is excluded from the absolute accuracy. Note 6-2: The conversion time refers to the period from the time when an instruction for starting a conversion process is issued to the time the conversion results register(s) are loaded with a complete digital conversion value corresponding to the analog input value.
No.A1536-21/28
LC87F1JJ2B
Consumption Current Characteristics at Ta = -40C to +85C, VSS1 = VSS2 = VSS3 = 0V
Parameter Normal mode consumption current (Note 7-1) IDDOP(2) Symbol IDDOP(1) Pin/ Remarks VDD1 =VDD2 =VDD3 Conditions VDD[V] * FmCF=12MHz ceramic oscillation mode * FsX'tal=32.768kHz crystal oscillation mode * System clock set to 12MHz side * Internal PLL oscillation stopped * Internal RC oscillation stopped * USB circuit stopped * 1/1 frequency division ratio IDDOP(3) * FmCF=12MHz ceramic oscillation mode * FsX'tal=32.768kHz crystal oscillation mode * System clock set to 12MHz side IDDOP(4) * Internal PLL oscillation mode active * Internal RC oscillation stopped * USB circuit active * 1/1 frequency division ratio IDDOP(5) IDDOP(6) IDDOP(7) IDDOP(8) IDDOP(9) IDDOP(10) IDDOP(11) IDDOP(12) IDDOP(13) HALT mode consumption current (Note7-1) IDDHALT(2) IDDHALT(1) * FmCF=12MHz ceramic oscillation mode * FsX'tal=32.768kHz crystal oscillation mode * System clock set to 6MHz side * Internal RC oscillation stopped * 1/2 frequency division ratio * FmCF=0Hz (oscillation stopped) * FsX'tal=32.768kHz crystal oscillation mode * System clock set to internal RC oscillation * 1/2 frequency division ratio * FmCF=0Hz (oscillation stopped) * FsX'tal=32.768kHz crystal oscillation mode * System clock set to crystal oscillation side (32.768kHz) * Internal RC oscillation stopped * 1/2 frequency division ratio * HALT mode * FmCF=12MHz ceramic oscillation mode * FsX'tal=32.768kHz crystal oscillation mode * System clock set to 12MHz side * Internal PLL oscillation stopped * Internal RC oscillation stopped * USB circuit stopped * 1/1 frequency division ratio IDDHALT(3) * HALT mode * FmCF=12MHz ceramic oscillation mode * FsX'tal=32.768kHz crystal oscillation mode * System clock set to 12MHz side IDDHALT(4) * Internal PLL oscillation mode active * Internal RC oscillation stopped * USB circuit active * 1/1 frequency division ratio IDDHALT(5) IDDHALT(6) IDDHALT(7) IDDHALT(8) IDDHALT(9) IDDHALT(10) * HALT mode * FmCF=12MHz ceramic oscillation mode * FsX'tal=32.768kHz crystal oscillation mode * System clock set to 6MHz side * Internal RC oscillation stopped * 1/2 frequency division ratio * HALT mode * FmCF=0Hz (oscillation stopped) * FsX'tal=32.768kHz crystal oscillation mode * System clock set to internal RC oscillation * 1/2 frequency division ratio 2.7 to 3.0 0.17 0.70 4.5 to 5.5 3.0 to 3.6 2.7 to 3.0 4.5 to 5.5 3.0 to 3.6 3.0 1.6 1.3 0.41 0.20 7.3 3.8 2.9 2.0 0.95 3.0 to 3.6 4.7 12 mA 4.5 to 5.5 9.5 23 3.0 to 3.6 2.7 6.4 4.5 to 5.5 4.9 12 2.7 to 3.0 4.5 to 5.5 3.0 to 3.6 2.7 to 3.0 4.5 to 5.5 3.0 to 3.6 2.7 to 3.0 3.6 0.77 0.43 0.36 47 19 15 8.2 3.7 2.0 1.6 184 65 51 A 4.5 to 5.5 3.0 to 3.6 7.2 4.4 17 11 3.0 to 3.6 8.0 21 mA 4.5 to 5.5 16 37 3.0 to 3.6 6.2 16 4.5 to 5.5 11 27 min Specification typ max unit
Note 7-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up resistors.
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No.A1536-22/28
LC87F1JJ2B
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Parameter HALT mode consumption current (Note 7-1) IDDHALT(13) IDDHALT(12) Symbol IDDHALT(11) Pin/ Remarks VDD1 =VDD2 =VDD3 * HALT mode * FmCF=0Hz (oscillation stopped) * FsX'tal=32.768kHz crystal oscillation mode * System clock set to crystal oscillation side (32.768kHz) * Internal RC oscillation stopped * 1/2 frequency division ratio HOLD mode consumption current Timer HOLD mode consumption current IDDHOLD(1) IDDHOLD(2) IDDHOLD(3) IDDHOLD(4) IDDHOLD(5) IDDHOLD(6) * Timer HOLD mode * CF1=VDD or open (External clock mode) * FsX'tal=32.768kHz crystal oscillation mode VDD1 * HOLD mode * CF1=VDD or open (External clock mode) 2.7 to 3.0 4.5 to 5.5 3.0 to 3.6 2.7 to 3.0 4.5 to 5.5 3.0 to 3.6 2.7 to 3.0 6.3 0.24 0.12 0.11 26 6.1 3.8 42 72 38 33 115 50 40 A 3.0 to 3.6 9.1 53 Conditions VDD[V] 4.5 to 5.5 min Specification typ 31 max 132 unit
Note 7-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up resistors.
USB Characteristics and Timing at Ta = -40C to +85C, VSS1 = VSS2 = VSS3 = 0V
Parameter High level output Low level output Output signal crossover voltage Differential input sensitivity Differential input common mode range High level input Low level input USB data rise time USB data fall time Symbol VOH(USB) VOL(USB) VCRS VDI VCM VIH(USB) VIL(USB) tR tF * RS=33, CL=50pF * RS=33, CL=50pF 4 4 * (UHD+)-(UHD-) Conditions min * 15k5% to GND * 1.5k5% to 3.6V 2.8 0.0 1.3 0.2 0.8 2.0 0.8 20 20 2.5 Specification typ max 3.6 0.3 2.0 unit V V V V V V V ns ns
F-ROM Programming Characteristics at Ta = +10C to +55C, VSS1 = VSS2 = VSS3 = 0V
Parameter Onboard programming current Programming time tFW(1) tFW(2) Symbol IDDFW(1) Pin/ Remarks VDD1 Conditions VDD[V] * Excluding power dissipation in the microcontroller block * Erase operation * Write operation 3.0 to 5.5 min Specification typ 5 20 40 max 10 30 60 unit mA ms s
3.0 to 5.5
Main System Clock Oscillation
The constant values of the oscillator and oscillation circuit for the main and system clocks must be determined after exercising extensive oscillation evaluation tests. For an application in which the USB host function is to be used, use an oscillator having the accuracy and precision that satisfy the USB specifications. The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized in the following cases (see Figure 4): * Till the oscillation gets stabilized after VDD goes above the operating voltage lower limit. * Till the oscillation gets stabilized after the instruction for starting the main clock oscillation circuit is executed. * Till the oscillation gets stabilized after the HOLD mode is released. * Till the oscillation gets stabilized after the X'tal HOLD mode is released with CFSTOP (OCR register, bit 0) set to 0.
No.A1536-23/28
LC87F1JJ2B
Subsystem Clock Oscillation
Table 1 shows the characteristics of a sample subsystem clock oscillation circuit that are measured using a SANYOdesignated oscillation characteristics evaluation board and external components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. Table 1 Characteristics of a Sample subsystem Clock Oscillator Circuit with a Crystal Oscillator
Nominal Frequency Vendor Name Oscillator Name C3 [pF] 32.768kHz EPSON TOYOCOM MC-306 18 Circuit Constant C4 [pF] 18 Rf [] OPEN Rd2 [] 560k Operating Voltage Range [V] Oscillation Stabilization Time typ [s] 1.1 max [s] Applicable CL 2.7 to 5.0 3.0 value=12.5pF SMD type Remarks
The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized in the following cases (see Figure 4): * Till the oscillation gets stabilized after the instruction for starting the subclock oscillation circuit is executed. * Till the oscillation gets stabilized after the HOLD mode is released with EXTOSC (OCR register, bit 6) set to 1. Note: The components that are involved in oscillation should be placed as close to the IC and to one another as possible because they are vulnerable to the influences of the circuit pattern.
CF1
CF2
XT1 Rf
XT2
Rd1
Rd2
C1
CF
C2
C3
X'tal
C4
Figure 1 CF Oscillator Circuit
Figure 2 Crystal Oscillator Circuit
0.5VDD
Figure 3 AC Timing Measurement Point
No.A1536-24/28
LC87F1JJ2B
VDD Operating VDD lower limit Power supply Reset time GND
RES
Internal RC oscillation tmsCF
CF1, CF2 tmsX'tal
XT1, XT2 Execute oscillation enable instruction. Operating mode Unpredictable Reset Instruction execution
Reset Time and Oscillation Stabilization Time
HOLD release signal
HOLD release signal valid
Internal RC oscillation
tmsCF
CF1, CF2 tmsX'tal * When oscillation is enabled before entry into HOLD mode XT1, XT2
Operating mode
HOLD
HALT
HOLD Release Signal and Oscillation Stabilization Time Figure 4 Oscillation Stabilization Time
No.A1536-25/28
LC87F1JJ2B
P34/UFILT
Rd 0k + Cd - 2.2F
When using the internal PLL circuit to generate the 48MHz clock for USB, it is necessary to connect a filter circuit to the P34/UFILT pin such as that shown in the left figure.
Figure 5 External Filter Circuit for the Internal USB-dedicated PLL Circuit
P33/AFILT
+ Cp 1F -
Rd 150 + Cd 4.7F
To generate the master clock for the audio interface using the internal PLL circuit, it is necessary to connect a filter circuit to the P33/AFILT pin that is shown in the left figure.
Figure 6 External Filter Circuit for Audio Interface (Used with Internal PLL Circuit)
33 UHD+ 5pF 15k
It is necessary to adjust the Circuit Constant of the USB Port Peripheral Circuit for each mounting board.
33 UHD5pF 15k
Figure 7 USB Port Peripheral Circuit
No.A1536-26/28
LC87F1JJ2B
VDD
RRES
RES CRES
Note: Determine the value of CRES and RRES so that the reset signal is present for a period of 200s after the supply voltage goes beyond the lower limit of the IC's operating voltage.
Figure 8 Reset Circuit
SIOCLK:
DATAIN:
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DI7
DI8
DATAOUT:
DO0
DO1
DO2
DO3
DO4
DO5
DO6
DO7 Data RAM transfer period (SIO0, 4, 9 only)
DO8
tSCK tSCKL SIOCLK: tsDI DATAIN: tdDO DATAOUT: Data RAM transfer period (SIO0, 4, 9 only) tSCKL SIOCLK: tsDI DATAIN: tdDO DATAOUT: thDI tSCKHA thDI tSCKH
Figure 9 Serial I/O Waveform
No.A1536-27/28
LC87F1JJ2B
tPIL
tPIH
Figure 10 Pulse Input Timing Signal Waveform
Voh Vcrs
D+
tr 90% 10% 90%
tr
10%
Vol
D-
Figure 11 USB Data Signal Timing and Voltage Level
VIH(1) min=0.3VDD+0.7V
tSCKR
tSCKR: Defined as the time period from the time the state of the output starts changing till the time it reaches the value of VIH(1).
Figure 12 Serial Clock Output Timing Signal Waveform
SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of SANYO Semiconductor Co.,Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor Co.,Ltd. product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellectual property rights which has resulted from the use of the technical information and products mentioned above.
This catalog provides information as of July, 2009. Specifications and information herein are subject to change without notice.
PS No.A1536-28/28

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